In an active matrix type liquid crystal display device using an active matrix substrate, liquid crystal is sealed between an opposite substrate and a TFT array substrate in which a gate electrode (Y-electrode) and a data electrode (X-electrode) are arranged in a matrix fashion. The opposite substrate is arranged opposite to a TFT array substrate. The thin film transistor (TFT) is arranged in a cross point of the gate and data electrodes. A voltage applied to the liquid crystal is controlled by the thin film transistor. Thus, the liquid crystal display is enabled to display an image by using an electrical optical effect of the liquid crystal.
As a structure of the active matrix substrate in which a thin film transistor is formed, a top gate type (a positive stagger type) structure and a bottom gate type (a reverse stagger type) structure have been known. In this top gate type active matrix substrate, a light shielding film is first formed on an insulating substrate such as a glass substrate, and an insulating film formed of silicon oxide (SiOx), silicon nitride (SiNx) or the like is formed on the light shielding film. A source electrode and a drain electrode that are metallic electrodes are formed on the insulating film with a channel gap therebetween, and a pixel electrode formed of indium tin oxide (hereinafter referred to as ITO) is formed so as to be connected to either the drain electrode or the source electrode. Furthermore, an amorphous silicon film (hereinafter referred to as an a-Si film) as a semiconductor film which covers the source electrode and the drain electrode, a gate insulating film formed of SiOx, SiNx or the like, and a gate electrode formed of aluminum (Al) or the like are formed on the pixel electrode in this order. A protection film (a passivation film) formed of SiNx or the like is formed on the gate electrode.
On the other hand, in the bottom gate type active matrix substrate, at first, a gate electrode is formed on an insulating substrate such as a glass substrate, and a gate insulating film and an a-Si film are formed on the gate electrode. Furthermore, a pixel electrode formed of ITO is formed on the insulating substrate. Thereafter, a source electrode and a drain electrode are formed on the a-Si film with a channel gap therebetween. At this time, either the source electrode or the drain electrode is connected to the pixel electrode.
As the steps for manufacturing these active matrix substrates, so called a 7 PEP (Photo Engraving Process) structure generally exists. For example, in the 7 PEP structure for manufacturing a top gate type TFT, a light shielding film is formed in a first PEP, and then a source electrode and a drain electrode, which are formed of ITO, are formed by patterning in a second PEP. Thereafter, a pixel electrode formed of ITO is formed in a third PEP. In a fourth PEP, an a-Si film and a first gate insulating film are formed by a CVD (Chemical Vapor Deposition), and patterned to an island-like pattern. Subsequently, a second insulating film is formed in a fifth PEP, and an Al film as a gate electrode is formed by sputtering and patterned in a sixth PEP. Finally, a protection film is formed in a seventh PEP.
Furthermore, in the seventh PEP for manufacturing a bottom gate type TFT, a gate electrode is formed on an insulating film by etching in the first PEP, and then a gate insulating, an a-Si film and an etching protection film formed of SiNx or the like are formed in the second PEP. In the third PEP, the a-Si film is patterned, and an a-Si island is formed. Subsequently, a pixel electrode formed of ITO is formed in the fourth PEP. Thereafter, perforation is performed so as to expose the gate electrode in the fifth PEP, and then a source electrode and a drain electrode are formed in the sixth PEP. Finally, the source electrode and the drain electrode are covered with a protection film formed of SiNx or the like in the seventh PEP, thus completing a series of steps.
However, the 7 PEPs structure is undesirable in a point that the 7 PEPs structure increases the number of complicated steps in addition to the number of photo masks, so that a yield ratio of the manufacturing steps is remarkably lowered, resulting in increase cost of the products. To solve such problems, the applicant of this application has proposed a technology relating to this manufacturing process as disclosed in Japanese Patent Application Numbers Hei 11(1998)-214603, Hei 12(2000)-4301 and Hei 12(2000)-28357. A 4 PEPs technology is adopted, in which a gate line undergoes over-etching in forming a gate electrode of a top gate type TFT, and a SiNx film and an a-Si layer are etched using a mask for forming the gate electrode. Thereby, conducting island cutting. Specifically, in the 4 PEP technology, the gate electrode, the gate insulating film and the a-Si film are sequentially etched by a single patterning step using a gate electrode plating pattern as a mask. The 4 PEPs technology has advantages, in that the manufacturing process steps can be reduced.
The PEP can be reduced by performing the island cutting process using the mask for forming the gate electrode. Resulting in an increased retention rate for the liquid crystal. More specifically, if dissolution of metal ions into the liquid crystal is reduced, and if portions of a data wiring and a gate wiring, which are exposed to the liquid crystal, can be reduced, the retention rate of the liquid crystal can be greatly increased. Furthermore, if adhesion of whiskers, dusts and the like to the liquid crystal can be reduced, it is possible to reduce the occurrence of a short-circuiting fault. Furthermore, if corrosion of a lead-out wiring can be reduced, a yield rate and a span in which products have reliability can be significantly increased.
Japanese Patent No. 2873119 discloses a technology in which patterning of an i-type semiconductor layer is made unnecessary. An n+ type semiconductor layer, a source electrode and a drain electrode are simultaneously patterned, thus reducing the number of photo masks used in patterning them. However, the technology disclosed in '119 results in a large number of layers, and etching processes becomes troublesome, leading to a low yield rate. Moreover, since the gate electrode cannot withstand etching of the gate insulating film, an ITO film is formed thereon. However, this further requires a further step of forming the ITO film, and it is impossible to achieve a satisfactory simplified manufacturing process.